Many conventional interface designs require both devices connected to either side of the interface to be in the same clock domain. For example, a processor and memory device may be required to be synchronized to the same clock in order for the processor to reliably access the memory. Clock synchronization is further required when there is a bidirectional interface between the two devices.
As a result, devices need to be in the same domain and thus must operate at higher frequencies as technology advances and the devices become faster. Therefore, it can be costly to pair devices (e.g., processor and memory) suitable for and operating in the same clock domain.
Prior art solutions have multiple clock domains have introduced additional latency or synchronization uncertainty and required first in first out (FIFO) access. The additional latency is often a result of one clock domain being slower than the other clock domain and the time required to synchronize. The difference in clock domains may also require FIFO access because operations in the faster domain need to wait for the operations in the slower domain.